Google and Facebook should make an update to their servers at the end of the year to coincide with the release of AMD's Interlagos and Romley, the new Sandy Bridge to server using an Intel Socket LGA 2011. According to DigiTimes, that would have received the information from manufacturers of servers, this phenomenon should create a wave of renewal of machinery and related products, such as storage devices or network devices.
Romley will integrate processors with eight cores supporting Hyper-Threading and dual processor motherboards for a maximum of 32 threads. The companies are now recovering from the economic crisis by assemblers, which are cited by DigiTimes. Their new economic health explains the desire to upgrade their infrastructure.
Intel showed the first Romley at IDF in September 2010. They integrate a memory controller with four channels of DDR3 compatible LRDIMM (Reduced Load Dual Inline Memory Modules) that enables systems using over 32 GB of memory to run each strip at its maximum frequency. The conventional controllers are unable to maintain the integrity of data in this kind of configuration due to signal deterioration that occurs when using all the memory chips.
With LRDIMM, Intel can support 96 GB of lossless frequency. The LRDIMM uses a buffer that reduces the flow of information flowing between the processor and memory. The bus is less taxed by the increase of memory modules. The LRDIMM is a derivative of technology MetaRAM. It encompasses virtually a series of memory chips in order to simplify the controller's task and increase the capacity of the bar.
For example, it is possible to place 32 modules of 125 MB for an array of 4 GB and the system sees only 8 chips of 500 MB can therefore put more modules on a bar. The problem is that the buffer required for the proper functioning of this technology is expensive, which explains that LRDIMM are primarily reserved for servers.
According to the rumors that circulated last month, the Sandy Bridge Romley use a L3 cache of 2.5 MB per core, totaling 20MB, and will have a TDP will be between 40 W and 95 W according applications of the system. They will be coupled with Intel Patsburg-B. The Romley should be marketed under the name Xeon E5.
They also will have two QPI links, 40 PCI-Express 3.0, DMI 2.0 4 lines. They are opposed to Interlagos AMD will be built on the Bulldozer architecture. They will integrate between twelve and sixteen cores, four-channel memory controller and 16 MB of L3 cache. They should be marketed at the same time that Romley. 
Romley will integrate processors with eight cores supporting Hyper-Threading and dual processor motherboards for a maximum of 32 threads. The companies are now recovering from the economic crisis by assemblers, which are cited by DigiTimes. Their new economic health explains the desire to upgrade their infrastructure.
Intel showed the first Romley at IDF in September 2010. They integrate a memory controller with four channels of DDR3 compatible LRDIMM (Reduced Load Dual Inline Memory Modules) that enables systems using over 32 GB of memory to run each strip at its maximum frequency. The conventional controllers are unable to maintain the integrity of data in this kind of configuration due to signal deterioration that occurs when using all the memory chips.
With LRDIMM, Intel can support 96 GB of lossless frequency. The LRDIMM uses a buffer that reduces the flow of information flowing between the processor and memory. The bus is less taxed by the increase of memory modules. The LRDIMM is a derivative of technology MetaRAM. It encompasses virtually a series of memory chips in order to simplify the controller's task and increase the capacity of the bar.
For example, it is possible to place 32 modules of 125 MB for an array of 4 GB and the system sees only 8 chips of 500 MB can therefore put more modules on a bar. The problem is that the buffer required for the proper functioning of this technology is expensive, which explains that LRDIMM are primarily reserved for servers.
According to the rumors that circulated last month, the Sandy Bridge Romley use a L3 cache of 2.5 MB per core, totaling 20MB, and will have a TDP will be between 40 W and 95 W according applications of the system. They will be coupled with Intel Patsburg-B. The Romley should be marketed under the name Xeon E5.
They also will have two QPI links, 40 PCI-Express 3.0, DMI 2.0 4 lines. They are opposed to Interlagos AMD will be built on the Bulldozer architecture. They will integrate between twelve and sixteen cores, four-channel memory controller and 16 MB of L3 cache. They should be marketed at the same time that Romley.
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