Wednesday, May 25, 2011

Detect the imperfections of a wafer faster

Semiconductor Research Corporation (SRC) and researchers at the University of Los Angeles (UCLA) presented a new technology for detecting a defective wafer faster. By installing the test structures during the early stages of manufacturing a die and then checking them immediately, it could save 15% on production costs and increase profits per chip by 12%, according to a statement published on the CBC website.

The work focuses on the wafer or wafer trimming pruning in English. This is the process of removing the outset defective slabs. Simply put, structures are etched between the dies at the beginning of the manufacturing process. They are easy to test and detect problems with electrical resistors or capacitors.

If a test components fails, it means that the structure is located in a region of the wafer which is experiencing a fault. The system can then isolate the area and focus on healthy areas. If the founder discovered that too much of the wafer is affected, it may decide to throw the wafer immediately.

It may therefore proceed to a wafer healthy faster, save time, money and materials. A wafer is a silicon wafer cut from a bar whose manufacture is highly complex and sensitive (cf. "Miniaturization of transistors and larger wafers: understanding technological issues). He has a monocrystalline structure that will serve as the foundation for the manufacture of transistors.

It then passes through various treatments after cutting and polishing to obtain a suitable structure. However, any malformation or the smallest defect will adversely affect the proper functioning of the transistors. An imperfection can order several diseases. Everything will depend on where it is and its importance.

Typically, the chip is completed before the launch of reliability tests, as CBC. The problem is that a defective chip because of a bad wafer is expensive because it has monopolized the production lines with no chance of success. It takes time and is wasteful. In making a preliminary analysis of the wafer, CBC says that one can detect 70% of the chips that are defective and pruning of wafers would be responsible for only a 1% decrease in yield.

Indeed, taking a full wafer, it also eliminates the functional chips, but in this case, the study states that the savings in time and money are so important that the gains overshadow the problem. SRC is a consortium comprising leading names in the semiconductor industry such as Intel, AMD, Globalfoundries, Freescale, Texas Instruments and Applied Materials.

Big Blue will test the method presented by CBC on its production lines in 45 nm, according to EETimes. It can then quantify the gains from this technology and confirm or refute the paper researchers.

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