Si2 consortium comprising the leading names in the semiconductor industry, announced work on Open3D Project, a standard to facilitate the design and manufacture chips that have dies stacked on each other. The list of members belonging to Si2 is long and includes the 95 major semiconductor companies in the world.
Of these, six have agreed to work on this new project (Advanced Semiconductor Engineering Inc.. (ESA), Altera Corp.. Analog Devices Inc.. (ADI), LSI Corp.., On Semiconductor Corp.. And Qualcomm Inc.). They join Globalfoundries, Hewlett Packard, Hynix, IBM, Intel, Samsung, and UMC, which are already in the game.
TSMC will be represented by ASE. As you can see, the big names in the industry address a problem that haunts them for years and that is how far you can push the FDP and similar technologies. Through the Silicon Via (TSV) is considered a method of making 3D as it is to die stacked on each other and join them by interconnections through the silicon layers to bind the story together.
There is also an assembly method called 2.5D where a silicon layer is interposed between two dies and the interconnects do not pass through the die, as the FDP, but around. For more information on this topic, we invite you to read our chapter "Architectural Solutions to challenges power" of our article, "Miniaturization of transistors and larger wafers: understanding technology issues." These methods are not new and are already used in memory chips (see "A smartphone is possible with 128 GB Toshiba") and CMOS image sensors.
However, except for those chips relatively simple terms lithographic 2.5D models and 3. D remain absent from smelters, forcing manufacturers to produce larger chips, which has a lot of inconvenience and limit the rise in performance. For now, the processors to HSV did not exceed the framework of scientific papers and PowerPoint presentations, but the consortium's mission is to just get things done.
The challenge is enormous through the manufacture of dies, their assembly, handling and integrating a package suitable to not overwrite everything. A standard would democratize the technology by putting them within reach of all industry players. Indeed, the founders are not the only ones concerned.
All stages of manufacturing a chip through the polishing of the wafer assembly and packaging where reliability testing must meet the new challenges that these methods. Why do these companies come together they now? For two reasons. The first is that advanced lithography allows to consider new structures.
The second is that the miniaturization of transistors and reached exorbitant sums to stack the dies means you can increase performance without necessarily investing in a new fine engraving. 
Of these, six have agreed to work on this new project (Advanced Semiconductor Engineering Inc.. (ESA), Altera Corp.. Analog Devices Inc.. (ADI), LSI Corp.., On Semiconductor Corp.. And Qualcomm Inc.). They join Globalfoundries, Hewlett Packard, Hynix, IBM, Intel, Samsung, and UMC, which are already in the game.
TSMC will be represented by ASE. As you can see, the big names in the industry address a problem that haunts them for years and that is how far you can push the FDP and similar technologies. Through the Silicon Via (TSV) is considered a method of making 3D as it is to die stacked on each other and join them by interconnections through the silicon layers to bind the story together.
There is also an assembly method called 2.5D where a silicon layer is interposed between two dies and the interconnects do not pass through the die, as the FDP, but around. For more information on this topic, we invite you to read our chapter "Architectural Solutions to challenges power" of our article, "Miniaturization of transistors and larger wafers: understanding technology issues." These methods are not new and are already used in memory chips (see "A smartphone is possible with 128 GB Toshiba") and CMOS image sensors.
However, except for those chips relatively simple terms lithographic 2.5D models and 3. D remain absent from smelters, forcing manufacturers to produce larger chips, which has a lot of inconvenience and limit the rise in performance. For now, the processors to HSV did not exceed the framework of scientific papers and PowerPoint presentations, but the consortium's mission is to just get things done.
The challenge is enormous through the manufacture of dies, their assembly, handling and integrating a package suitable to not overwrite everything. A standard would democratize the technology by putting them within reach of all industry players. Indeed, the founders are not the only ones concerned.
All stages of manufacturing a chip through the polishing of the wafer assembly and packaging where reliability testing must meet the new challenges that these methods. Why do these companies come together they now? For two reasons. The first is that advanced lithography allows to consider new structures.
The second is that the miniaturization of transistors and reached exorbitant sums to stack the dies means you can increase performance without necessarily investing in a new fine engraving.
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