Texas Instruments and the Massachusetts Institute of Technology will present a paper during the International Solid-State Circuits Conference (ISSCC), detailing a mobile processor for low-voltage application etched into 28 nm. This DSP (Digital Signal Processor) is able to move from a mode called High Performance consuming 1 V at a level requiring only low power 0.6 V.
The CSP is built on a TI TMS320C64x uses the VLIW instruction set of 256 bits and can support 32 registers of 32 bit words. The SoC has a 32 KB L1 cache and a second level cache of 128 KB, an interface for managing an external memory and MMC memory cards. The operating frequency range from 587 MHz to 43.4 MHz.
Some colleagues on the web to compare processor SoC ARM that make the headlines at the moment. It is our opinion a false comparison, because while a DSP in 28 nm is a breakthrough technology, it is not at all or the same architecture complexity and the two chips have features very different. 
The CSP is built on a TI TMS320C64x uses the VLIW instruction set of 256 bits and can support 32 registers of 32 bit words. The SoC has a 32 KB L1 cache and a second level cache of 128 KB, an interface for managing an external memory and MMC memory cards. The operating frequency range from 587 MHz to 43.4 MHz.
Some colleagues on the web to compare processor SoC ARM that make the headlines at the moment. It is our opinion a false comparison, because while a DSP in 28 nm is a breakthrough technology, it is not at all or the same architecture complexity and the two chips have features very different.
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