Samsung has just introduced a new memory that could solve one problem and therefore SoC ARM smartphones and other tablets: memory bandwidth. The new "Mobile DRAM With Wide I / O bus actually uses a memory of 512 bits, 32 bits with the cons LPDDR2 usually used. Samsung announced that its 1-gigabit chips etched into 50 nm can achieve a throughput of 12.8 GB / s, which indicates a relatively low operating frequency (equivalent to DDR2-200).
The advantage is that the bandwidth is correct with a sharp decline in consumption, Samsung speaking of 87% reduction in consumption. The Korean company hopes to produce chips with 4 Gigabit etched 20 nm in 2013, obviously with SoC compatible. The only problem is the physical connection: memory interfaces currently with 1200 pins.
Note that if the majority of today's SoC work with memory LPDDR2 on a 32 bit bus, the next generation should pass in 64-bit versions for the tablets will support DDR3 memory, the remaining LPDDR2 memory of choice smartphones, thanks to its consumption. 
The advantage is that the bandwidth is correct with a sharp decline in consumption, Samsung speaking of 87% reduction in consumption. The Korean company hopes to produce chips with 4 Gigabit etched 20 nm in 2013, obviously with SoC compatible. The only problem is the physical connection: memory interfaces currently with 1200 pins.
Note that if the majority of today's SoC work with memory LPDDR2 on a 32 bit bus, the next generation should pass in 64-bit versions for the tablets will support DDR3 memory, the remaining LPDDR2 memory of choice smartphones, thanks to its consumption.
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